1. Field of the Invention
The present invention relates to serial bus experimental apparatus and more particularly to serial bus experimental apparatus that allows the capturing of a series of massive packets transferred over a serial bus and their processing such as display, and/or that allows the transmission of a packet including an error to a node instrument to be tested.
2. Related Background Art
In recent years, the serial bus named IEEE 1394 (hereinafter, called as xe2x80x9cHigh Performance Serial Busxe2x80x9d) has been in practical use. This bus has allowed a personal computer to be connected with printers, digital cameras, external hard disks and the like in a daisy chain or in a tree structure, so that high speed communication between any node instruments has been allowed. The high performance serial bus features that a large number of node instruments can be connected with a small cable and further a massive amount of data, such as dynamic image data, can be easily transferred through the small cable.
As shown in FIG. 6, a high performance serial bus 1 comprises serial bus cables 11-1nxe2x88x921 connecting a plurality of node instruments 21-2n in serial. Each node instrument 2i includes physical layer circuit 4i and link layer circuit 5i which perform protocol control for serial communication in hardware level according to instructions of the high order controller 3i. The physical layer circuit 4i is connected to serial bus cables 1ixe2x88x921, 1i. When the physical layer circuit 4i receives a transmission signal transmitted over the serial bus cable 1ixe2x88x921 (or 1i) from other node instrument, it outputs the same transmission signal to the serial bus cable 1i (or 1ixe2x88x921). At the same time, the physical layer circuit 4i also converts the transmission signal to reception data, and outputs the reception data to the link layer circuit 5i. Further, when the physical layer circuit 4i receives transmission data from the link layer circuit 5i, it converts the transmission data to a transmission signal and outputs the transmission signal through the serial bus cables 1ixe2x88x921 and 1i.
The link layer circuit 5i produces a transmission packet destined for other node instrument according to instructions of the high order controller 3i and outputs a transmission data stream composing the transmission packet to the physical layer circuit 4i. Specifically, in the case of an isochronous packet for which transfer of 125 micro-second-cycle is guaranteed, upon receipt of header information including data lengths, channel numbers and synchronization codes and data from the controller 3i, the link layer circuit 5i produces an isochronous packet (see FIG. 7), conforming to a predetermined format, composed of an integral multiple of four bytes while adding a header CRC and data CRC, obtained by calculation, for error detection/correction and the like. Then, it outputs to the physical layer circuit 4i the transmission data row from the first bit of it in groups of 2 bits (a transfer speed of 100 Mbps), in groups of 4 bits (a transfer speed of 200 Mbps) or in group of 8 bits (a transfer speed of 400 Mbps). In the case of an asynchronous packet that is transferred asynchronously, there are some differences such that a destination ID and source ID are added to the header information as a substitute for the channel number and the like.
Further, when the link layer circuit 5i receives a reception data stream from the physical layer circuit 4i, it takes out a reception packet for its own node to capture from the data rows and outputs the packet to the controller 3i. The link layer circuit 5i and the physical layer circuit 4i receive and transmit control signals through three control lines CTL0, CTL1 and LReq, and also receives and transmits transmission data or reception data by handshaking using two lines D0 and D1 of eight data lines D0-D7 (in the case of a transfer speed of 100 Mbps), four lines D0-D3 (in the case of a transfer speed of 200 Mbps) and eight lines D0-D7 (above 400 Mbps). In addition, the physical layer circuit 4i performs bus arbitration at the time of transmission and also outputs a clock SCLK synchronized with the control signals and data which are transmitted to the link layer circuit 5i or received from it.
Serial bus experimental apparatus for carrying out performance tests on various node instruments connected to the high performance serial bus has been developed. The serial bus test apparatus, as shown by a reference numeral 2n in FIG. 6, is also connected to the bus as one of node instruments in the same way as the other node instruments. It also includes a controller 3n for a bus test comprising a microprocessor for example, a link layer circuit 5n, a physical layer circuit 4n, a memory 10, a display 11 and a operational panel 12. For example, when it is desired to test on a node instrument 21 which performs isochronous transfer on a channel number 1, the following have been stored in the memory 10 in advance. That is, various test data to be used in a test on the node instrument 21, the channel number on which the node instrument 21 performs isochronous transfer, the ID of the node instrument 21, the ID of the serial bus experimental apparatus and the like.
When the activation of the node instrument 21 is directed through the operational panel 12, the controller 3n outputs the following to the link layer circuit 5n, referring to the memory 10. That is, header information including a transfer speed (here, assumed to be 100 Mbps), the destination ID which is the ID of the node instrument 21, the source ID which is the ID of the serial bus experimental apparatus and the data length of the asynchronous packet, and data including the activation instruction. The link layer circuit 5n produces an asynchronous packet (FIG. 5) conforming to a predetermined format adding a header CRC, data CRC and the like and, at the same time, notices transmission request and the transfer speed to the physical layer circuit 4n through the control line LReq. Then, when the physical layer circuit 4n wins the arbitration of access to the high performance serial bus and provides transmission permission for the link layer circuit 5n through the control lines CTL0, CTL1, the link layer circuit 5n outputs to the physical layer circuit 4n the transmission data in groups of two bits from the first of the asynchronous packet using the data line D0 and D1 in synchronization with the clock SCLK. At this moment, the link layer circuit 5n outputs over the control lines CTL0, CTL1 a control signal to indicate that transmission data is being outputted.
The physical layer circuit 4n receives the transmission data, converts the data to an electrical transmission signal conforming to the standard and outputs the signal to the high performance serial bus.
When the link layer circuit 5n has finished outputting a packet of transmission data and has no packet to transmit, it outputs a control signal to indicate the completion of transmission over the control lines CTL0, CTL1. Receiving the control signal, the physical layer circuit 4n shifts to another processing.
When the node instrument 21 receives the asynchronous packet of the transmission signal transmitted from the serial bus experimental apparatus 2n and transmits back an isochronous packet of a transmission signal at a transfer speed of 100 Mbps in a fixed cycle, the physical layer circuits 42-4n in all the other node instruments 22-2n receive the transmission signal and convert it to reception data and output it to the link layer circuits 52-5n. At this moment, the physical layer circuits 42-4n output over the control lines CTL0, CTL1 control signals to indicate that the reception data is being outputted.
When the control signals to indicate that the reception data is being outputted are on the control lines CTL0, CTL1, the link layer circuits 52-5n receive the reception data in synchronization with the clock SCLK and reconstitutes the reception packet while performing error detection/correction by using the header CRC and data CRC. And, because it is an isochronous packet, the link layer circuits 52-5n check if the channel number included in the head is the number of which reception is directed by the high order controllers. If it is the number directed, the isochronous packet is outputted to the high order controllers. If it is not the number directed, this reception packet is ignored. Concerning the serial bus experimental apparatus 2n, if it is assumed that the channel number in the head has been directed by the controller 3n, in advance, the link layer circuit 5n outputs the reception packet from the node instrument 21 to the controller 3n. Then, the controller 3n has the reception packet stored in the memory 10. Each time an isochronous packet is repeatedly received from the node instrument 2i, the same processing is repeated.
If display is instructed through the operational panel 12, the controller 3n has the reception packet stored in the memory 10 to be displayed on the display 11 and allows an operator to check it.
By the way, in the case of a test on a node instrument connected to a serial bus, it is necessary to check whether the node instrument to be tested correctly transmits and receives packets or not. For this purpose, it is necessary to monitor all packets transmitted over the bus.
Some link layer circuits have the snoop function by which link layer circuits capture all reception packets from the reception data streams inputted from physical layer circuits and output them to the controllers. However, in order that a controller can transmit desired packets destined for other node instruments in parallel with the capture of a large amount of packets, a very high processing speed is required and so the load from the viewpoint of the system configuration is heavy. Further, because the packets captured by the snoop function of a link layer circuit do not include transmission packets, it is impossible to monitor in time sequence all packets transmitted over a serial bus.
Further, when it is desirable to carry out a performance test such that a packet intentionally including a wrong value of data length or a wrong header CRC or a wrong data CRC is transmitted to a node instrument 21 to be tested, it is very difficult to actually perform such a test using link layer circuits 5n on the market in general. Because, link layer circuits 5n on the market produce automatically a correct packet in conformance with the standard. Therefore, it is necessary to make a particular link layer circuit to provide an error packet.
Considering the problems described above of conventional technology, an object of the present invention is to provides a serial bus experimental apparatus which has a simple configuration and allows all packets of a series of packets transmitted over a serial bus to be captured. Another object of the invention is to provide a serial bus experimental apparatus that has a simple configuration and allows forcing an error to occur for carrying out a performance test on a target instrument. Further another object of the invention is to provide a serial bus experimental apparatus comprising both functions above described.
A serial bus experimental apparatus in accordance with a first aspect of the invention includes a physical layer circuit connected to a serial bus, receiving a transmission signal transmitted over the serial bus from other node instrument, converting the transmission signal to reception data and outputting the data, and converting transmission data to a transmission signal for transmitting the transmission signal over the serial bus, and a link layer circuit connected to the physical layer circuit, according to an instruction from a controller for a test on the serial bus, producing a transmission packet destined for other node instrument, outputting transmission data making up a transmission packet to the physical layer circuit, and further comprises a memory means for allowing the controller for a test on the serial bus to read out the contents of the memory and to perform predetermined processing thereon, and a packet capture means connected to data output sides of the physical layer circuit and the link layer circuit, receiving reception data and transmission data outputted from the physical layer circuit and said link layer circuit, and enforcing a series of packets received and transmitted between the physical layer circuit and the link layer circuit to be stored in the memory means.
The physical layer circuit receives a transmission signal transmitted over the serial bus from other node instruments and converts the transmission signal to transmission data and outputs the data. Further, the link layer circuit, according to an instruction of the controller for a test on the serial bus, produces a transmission packet destined for other node instrument and outputs transmission data making up the transmission packet to the physical layer circuit. The packet capture means receives reception data and transmission data outputted from the physical layer circuit and the link layer circuit, respectively, and enforces a series of packets received and transmitted between the physical layer circuit and the link layer circuit to be stored in the memory means. The controller for a test on serial bus reads out the series of packets stored in the memory means and performs predetermined processing thereon such as a display and printing so as for them to be available for a operator.
Thereby, it is allowed to store into the memory means a series of packets transmitted over the serial bus including a packet transmitted from the serial bus experimental apparatus through a separate path from the path for the controller for a test on serial bus. Therefore, without the need for a controller with capability of high speed processing, the serial bus experimental apparatus allows the transmission of a desired packet for other node instrument, while capturing massive packets transmitted over the serial bus.
The serial bus experimental apparatus in accordance with the first aspect of the invention provides a reference packet set up means for setting a packet of reference for capture and the packet capture means for enforcing packets in a specified time relationship with the reference packet set by the set up means to stored in the memory means.
This allows the capture of packets in any desired time period necessary for analysis, such as a period before and after the transmission of a packet for a node instrument to be tested.
Further, the packet capture means stores the timing information of the packets.
This allows the analysis of timing of packets transmitted over the serial bus together.
The serial bus experimental apparatus in accordance with the first aspect of the invention includes a physical layer circuit connected to a serial bus, receiving a transmission signal transmitted over the serial bus from other node instrument, converting the transmission signal to reception data, and converting transmission data to a transmission signal for transmitting the transmission signal over said serial bus, and a link layer circuit connected to the physical layer circuit, according to an instruction from a controller for a test on the serial bus, producing a transmission packet destined for other node instrument, outputting transmission data making up the transmission packet to the physical layer circuit. The physical layer circuit and the link layer circuit receive and transmit a control signal through a control line and receive and transmit data by handshaking. Further, the apparatus comprises a memory means for allowing the controller for a test on the serial bus to read out the contents of the memory and to perform predetermined processing thereon, and a packet capture means connected to data output sides and to control signal output sides of the physical layer circuit and the link layer circuit, receiving reception data and a control signal outputted from the physical layer circuit and transmission data and a control signal outputted from the link layer circuit, and enforcing a series of packets received and transmitted between the physical layer circuit and the link layer circuit to be stored associated with the control signal data in time relationship stored in said memory means.
The physical layer circuit receives a transmission signal transmitted over a serial bus from other node instrument and converts the transmission signal to transmission data and outputs the data. Further, the link layer circuit, according to the instruction of the controller for a test on the serial bus, produces a transmission packet destined for other node instrument and outputs transmission data making up a transmission packet to physical layer circuit. At this moment, the physical layer circuit and the link layer circuit receive and transmit a control signal through a control line and receive and transmit data by handshaking. The packet capture means receives reception data and a control signal outputted from the physical layer circuit and transmission data and a control signal outputted from the link layer circuit and enforces a series of packets received and transmitted between the physical layer circuit and the link layer circuit to be stored associated with control signal data in time relationship stored in the memory means. The controller for a test on the serial bus reads out the series of packets and control signal data stored in the memory means and performs predetermined processing thereon, such as a display and printing.
Thereby, in addition to a series of packets transmitted over a serial bus including a packet transmitted from the serial bus experimental apparatus, it is allowed to capture the control signal data received and transmitted between the physical layer circuit and the link layer circuit in association with the packet. So, more advanced analysis is allowed.
Further, a reference packet set up means for setting a packet of reference for capture is provided, and the packet capture means stores packets in a specified time relationship with the reference packet set by the set up means together with corresponding control signal data in the memory means.
Thereby, it is possible to capture packets and control signal data in any desired time period required for analysis such as a period before and after the transmission of a packet for a node instrument to be tested.
Further, the packet capture means stores timing information of the packet together stored.
Thereby, it is possible to analyze the timing of the packet transmitted over the serial bus.
A serial bus experimental apparatus in accordance with a second aspect of the invention includes a physical layer circuit connected to a serial bus, receiving a transmission signal transmitted over the serial bus from other node instrument, converting the transmission signal to reception data, and converting transmission data to a transmission signal for outputting the transmission signal over said serial bus, and a link layer circuit connected to said physical layer circuit, according to an instruction from the controller for a test on the serial bus, producing a transmission packet destined for other node instrument, outputting a transmission data stream making up the transmission packet to said physical layer circuit, receiving a reception data stream from said physical layer circuit, taking out therefrom a predetermined packet for outputting the packet to the controller for a test on the serial bus. Further, the apparatus comprises a transmission error creation circuit provided between the physical layer circuit and the link layer circuit and, when the link layer circuit produces a transmission packet destined for other node instrument and outputs the packet, while converting a portion of the transmission data stream making up the transmission packet to different data, inputs the different data to the physical layer circuit.
When the link layer circuit produces and outputs a transmission packet for other node instrument, this serial bus experimental apparatus converts a portion of the packet to different data and inputs the different data to the physical layer circuit, at the same time.
This allows a simple configuration without a particular link layer circuit to transmit a packet including an error and to carry out an operating test when the error packet is received.
In the serial bus experimental apparatus in accordance with the second aspect of the present invention, the transmission error creation circuit includes an error creation position set up means for setting an error creation position in the transmission packet and a position detection means which, for each transmission data of the transmission packet outputted from the link layer circuit, detects each corresponding position within the transmission packet, and a data change means which, when the position detected by the position detection means does not match with the error creation position set by the error creation position set up means, inputs the transmission data outputted from the link layer circuit to the physical layer circuit as it is, and when the position detected by the position detection means matches with the error creation position set by the error creation position set up means, replaces the transmission data outputted from the link layer circuit with different data and inputs the different data to physical layer circuit.
In accordance with this serial bus experimental apparatus, for each transmission data outputted from a transmission packet, each corresponding position within the transmission packet is detected by the position detection means, and, when the position does not match with the error creation position set by the error creation position set up means, the transmission data outputted from the link layer circuit is inputted to the physical layer circuit as it is and, when the position detected by the position detection means matches with the error creation position set by the error creation position set up means, the transmission data outputted from the link layer circuit is replaced with different data and the different data is outputted to the physical layer circuit.
Thereby, it is possible to enforce an error to occur at any desired position by changing an error creation position in the packet set by the error creation position set up means, and so a wide spectrums of tests is allowed.